1. Field of the Invention
The present invention relates to a multiprocessor system containing a plurality of processors and a networking apparatus which establishes physical links between the plurality of processors.
2. Description of the Related Art
In some types of parallel processing systems containing a plurality of processors, a networking apparatus is provided for transferring data between the plurality of processors. The networking apparatus receives a connection request from one of the plurality of data processing apparatuses, and establishes a physical link between the processor which sends the connection request to the networking apparatus and another of the plurality of data processing apparatuses which is requested by the connection request. Usually, in such a networking apparatus, a plurality of jobs are concurrently executed, and a processor on a receiving side may go into an off-line state during a data transfer operation from the other processor to the processor on the receiving side due to some cause. In such a case, the data transfer stops in a data route in the networking apparatus, and such a stop of a data transfer in a route in the networking apparatus affects the total operation of the networking apparatus, and thus affects the other data transfer operations through the networking apparatus.
FIG. 1 is a diagram illustrating an outlined construction of a multiprocessor system to which the present invention is applied. In FIG. 1, reference numerals 11 to in each denote a processor, 2' denotes a networking apparatus, and 3 denotes a service processor. The plurality of processors 1.sub.1 ' to 1.sub.n ' respectively execute jobs assigned to them under control of the service processor 3, in the manner of parallel processing. The networking apparatus 2 establishes a physical link between such processors for data transfers between the processors.
FIG. 2 is a diagram illustrating an outlined construction of a multiprocessor system to which the present invention is applied. In FIG. 2, reference numerals 101.sub.1, 101.sub.2 . . . 101.sub.n each denote a processor on the transmitting side, 2' denotes a networking apparatus, 4 denotes a switch unit, 5.sub.1 ', 5.sub.2 ', . . . 5.sub.n ' each denote a data transfer control unit, and 102.sub.1, 102.sub.2 . . . 102.sub.n each denote a processor on the receiving side. In FIG. 2, portions of the processors 1.sub.1 ' to 1.sub.n ' of FIG. 1 containing functions of transmitting data are respectively indicated as the processors 101.sub.1, 101.sub.2 . . . 101.sub.n on the transmitting side, and portions of the processors 1.sub.1 ' to 1.sub.n ' containing functions of receiving data are respectively indicated as the processors 102.sub.1, 102.sub.2 . . . 102.sub.n on the receiving side. The networking apparatus 2 contains the switch unit 4 and a plurality of data transfer control units 5.sub.1 ', 5.sub.2 ', . . . 5.sub.n ' provided corresponding to the respective processors 102.sub.1, 102.sub.2 . . . 102.sub.n on the receiving side. The switch unit 4 has a plurality of transmitting-side ports corresponding to the plurality (n) of the processors 101.sub.1, 101.sub.2 . . . 101.sub.n on the transmitting side, and a plurality of receiving-side ports corresponding to the plurality (n) of the processors 102.sub.1, 102.sub.2 . . . 102.sub.n on the receiving side. The switch unit 4 receives one or more connection requests with route information from one or more processors, and establishes a physical link (a route for a data transfer) from each transmitting-side processor to a corresponding receiving-side processor after priority control in response to the connection requests. Each data transfer control unit 5.sub.1 ', 5.sub.2 ', . . . 5.sub.n ' receives at an input port thereof data transferred from a corresponding one of the transmitting-side processors 101.sub.1, 101.sub.2 . . . 101.sub.n through the switch unit 4, and connects each output port thereof with a corresponding one of the receiving-side processors 102.sub.1, 102.sub.2 . . . 102.sub.n. Each data transfer control unit 5.sub.1 ', 5.sub.2 ', . . . 5.sub.n ' contains a data buffer circuit for temporarily storing data received as above, and transfers the temporarily stored data to the corresponding receiving-side processor when the data transfer control unit receives a transfer allowance signal transmitted from the corresponding receiving-side processor. Each data transfer control unit further contains a counter for counting an amount of data currently stored in the data buffer circuit. The count of the counter is incremented when the data is newly stored in the data buffer circuit, and is decremented every time a unit amount of data is transferred from the data buffer circuit to the corresponding receiving-side processor. When the count of the counter reaches a predetermined maximum allowable value, the data transfer is stopped.
However, when one of the receiving-side processors 102.sub.1, 102.sub.2 . . . 102.sub.n fails during the data transfer operation, the receiving-side processor cannot transmits the transfer allowance signal to the corresponding data transfer control unit. Therefore, the count of the counter reaches the predetermined maximum value, and data transfer is stopped in the data transfer control unit and this causes the data transfer control unit to hang up. In conventional networking apparatuses, it is necessary to reset the whole networking apparatus to recover a data transfer route through a hung-up data transfer control unit. Therefore, all of the data transfer operations for all of the other jobs must to be stopped due to the hang-up in one route (data transfer control unit).